The present invention relates to integrated semiconductor devices, and more particularly to an integrated semiconductor circuit that includes a planar single gate complementary metal oxide semiconductor (CMOS) device; and a double gate device, i.e., FinFET, which are fabricated on the same semiconductor substrate. In one instance, the planar single gate CMOS device is an nFET formed on a thin silicon-on-insulator (SOI) layer and the FinFET is a pFinFET structure having a vertical channel that has a surface orientation at the (110) direction. Alternatively, the planar single gate CMOS device is a pFET formed on a thin SOI layer with a (110) surface orientation and the FinFET is an nFinFET structure having a vertical channel that has a surface (100) orientation. The present invention also provides a method for fabricating the integrated semiconductor circuit of the present invention.
In present semiconductor technology, complementary metal oxide semiconductor (CMOS) devices, such as nFETs, and pFETs, are typically fabricated upon semiconductor wafers in the direction of a single surface orientation. In particular, most semiconductor devices are fabricated on a Si substrate so as to have a (100) surface orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4× lower than the corresponding electron hole mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths In order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching; nFETs with larger widths are undesirable since they take up a significant amount of chip area. On the other hand, hole mobilities on (110) Si are 2×higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pF Ts formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.
Conventional pFETs and nFETs are planar single gate devices that typically have poor sub-threshold voltage characteristics and drive currents for very short channel lengths, compared to double gated devices. Double gated structures offer improved sub-threshold characteristics; and drive currents as compared with conventional planar devices. One type of double-gated device of particular importance is the FinFET. A FinFET is a double-gated device that comprises a tall, yet thin vertical channel region.
Due to the vertical channel structure, a wafer with a (100) surface orientation can be used to fabricate FinFETs with a (110) channel surface orientation. In this case, the pFinFET experiences enhanced mobility with respect to the conventional CMOS device fabricated on a wafer with a (100) surface orientation. However, the nFinFET fabricate on the (100) surface orientation experiences mobility degradation compared to a conventional nFET on the (100) surface channel orientation.
Although it is known to form different types of planar single gated devices or different types of double gated devices on a semiconductor wafer, there exists a need to integrate both planar and FinFET devices on the same wafer in such a fashion that the devices are formed with a surface orientation that enhances the performance of each device. In particular, there is a need for providing an integrated semiconductor circuit that includes at least one nFET as the planar CMOS device and at least one pFinFET as the other device. The pFinFET should be fabricated such that the structure has a surface channel that is oriented at the (110) direction. Alternatively, there is a need for providing a circuit that is comprised of an nFinFET fabricated on a wafer with a (110) surface orientation so that the nFinFET has a (100) surface orientation and a planar pFET device having a (110) surface orientation.